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Freescale Semiconductor Hardware Specification
MCF5275EC/D Rev. 1.1, 9/2004
MCF5275 Integrated Microprocessor Family Hardware Specification
32-Bit Embedded Controller Division
The MCF5275 family is a highly integrated implementation of the ColdFire(R) family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions characteristics of the MCF5275 family. The MCF5275 family includes the MCF5275, MCF5275L, MCF5274 and MCF5274L microprocessors. The differences between these parts are summarized in Table 1. This document is written from the perspective of the MCF5275 and unless otherwise noted, the information applies also to the MCF5275L, MCF5274 and MCF5274L. The MCF5275 family delivers a new level of performance and integration on the popular version 2 ColdFire core with up to 159 (Dhrystone 2.1) MIPS @ 166MHz. These highly integrated microprocessors build upon the widely used peripheral mix on the popular MCF5272 ColdFire microprocessor (10/100 Mbps Ethernet MAC and USB device) by adding a second 10/100 Mbps Ethernet MAC (MCF5274 and MCF5275) and hardware encryption (MCF5275L and MCF5275). In addition, the MCF5275 family features an Enhanced Multiply Accumulate Unit (EMAC), large on-chip
Table of Contents
1 2 3 4 5 6 7 8 9 10 11 12 MCF5275 Family Configurations ..................... 2 Block Diagram ................................................. 3 Features .......................................................... 5 Signal Descriptions........................................ 17 Chip Configuration......................................... 32 Design Recommendations ............................ 34 Pinout ............................................................ 42 Mechanicals .................................................. 45 Ordering Information ..................................... 47 Preliminary Electrical Characteristics ............ 47 Device/Family Documentation List ................ 74 Document Revision History ........................... 74
Technical Data (c) Freescale Semiconductor, Inc., 2004. All rights reserved. * Preliminary
MCF5275 Family Configurations
memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory controller. These devices are ideal for cost-sensitive applications requiring significant control processing for file management, connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security, imaging, networking, gaming, and medical. This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support. To locate any published errata or updates for this document, refer to the ColdFire products website at http://www.freescale.com.
1
MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module
ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit) System Clock Performance (Dhrystone 2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) DDR SDRAM Controller Fast Ethernet Controller (FEC) Watchdog Timer Module (WDT) 4-channel Programmable Interval Timer Module (PIT) 32-bit DMA Timers USB QSPI UART(s) I2 C 2 x x x x 1 x x 4 x x 3 x 4 x x
5274L
x
5275L
x
5274
x
5275
x
up to 166 MHz up to 159 16 Kbytes (configurable) 64 Kbytes 2 x x x x 1 x x 4 x x 3 x 4 x x 2 x x x x 2 x x 4 x x 3 x 4 x x 2 x x x x 2 x x 4 x x 3 x 4 x x
PWM General Purpose I/O Module (GPIO) CIM = Chip Configuration Module + Reset Controller Module
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 2 Preliminary Freescale Semiconductor
Block Diagram
Table 1. MCF5275 Family Configurations
Module
Debug BDM JTAG - IEEE 1149.1 Test Access Port Hardware Encryption Package
5274L
x x -- 196 MAPBGA
5275L
x x x 196 MAPBGA
5274
x x -- 256 MAPBGA
5275
x x x 256 MAPBGA
2
Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 3
Block Diagram
DDR
EIM (To/From SRAM backdoor) CHIP SELECTS
QSPI I2C_SDA I2C_SCL TXDx RXDx
EBI Arbiter INTC0 INTC1
RTSx CTSx DTOUTx DTINx
PADI - Pin Muxing
(To/From PADI)
FAST ETHERNET CONTROLLER (FEC0) FAST ETHERNET CONTROLLER (FEC1) UART 0 UART 1 UART 2 I2 C QSPI SDRAMC
FEC0 FEC1 USB PWMx D[31:16] A[23:0] R/W CS[3:0]
(To/From PADI)
(To/From PADI)
DTIM 0 4 CH DMA
DTIM 1
DTIM 2
DTIM 3
TA JTAG_EN TRST
JTAG TAP
BDM
DREQ[1:0]
DACK[3:0]
V2 ColdFire CPU
DIV EMAC
TCLK TMS TDI TDO
MUX
TSIZ[1:0] JTAG_EN TEA BS[3:2]
(To/From PADI) (To/From PADI) 4 CH PWM
64 Kbytes SRAM (8Kx16)x4
16 Kbytes CACHE (1Kx32)x4 PORTS (GPIO) CIM
Watchdog Timer
(To/From Arbiter backdoor)
SKHA USB 2.0 Full Speed
PLL CLKGEN (To/From INTC)
PIT0
PIT1
PIT2
PIT3
RNGA
MDHA Cryptography Modules
(To/From PADI)
Edge Port
Figure 1. MCF5275 Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 4 Preliminary Freescale Semiconductor
Features
3
Features
This document contains information on a new product. Specifications and information herein are subject to change without notice.
3.1
*
Feature Overview
ColdFire version 2 variable-length RISC processor -- Static operation -- 32-bit address and data path on-chip -- 166/133 MHz processor core and 83/66.5 MHz bus frequency -- Sixteen general-purpose 32-bit data and address registers -- Enhanced multiply accumulate unit (eMAC) for DSP and fast multiply operations System debug support -- Real time trace for determining dynamic execution path while in emulator mode -- Background debug mode (BDM) for debug features while halted -- Real time debug support, with two user visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger On chip memories -- 16 Kbyte cache, configurable as I-cache or I-cache and D-cache -- 64 Kbyte dual-ported SRAM on CPU internal bus with standby power supply support Power management -- Fully static operation with processor sleep and whole chip stop modes -- Very rapid response to interrupts from the low-power sleep mode (wake-up feature) Two Fast Ethernet Media Access Controllers (FEC MAC) -- 10 base T capability, half or full duplex -- 100 base T capability, half or full duplex throughput -- On chip transmit and receive FIFOs -- Built-in DMA controller -- Memory-based flexible descriptor rings -- Media independent interface (MII) USB Device Module -- Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB devices -- Full compliance with the Universal Serial Bus Specification, Revision 2.0 -- Automatic hardware processing of USB standard device requests -- Supports external USB transceiver -- Protocol control and administration for up to four endpoints (programmable types)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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*
*
*
*
Freescale Semiconductor
Preliminary
5
Features
*
*
*
*
* * *
-- One FIFO RAM per endpoint (2-Kbyte total) -- Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus -- Remote wake-up Hardware cryptography accelerator (optional) -- Random number generator -- DES/3DES/AES block cipher engine -- MD5/SHA-1/HMAC accelerator Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs) -- Serial communication channel -- 16-bit divider for clock generation -- Internal channel control logic -- Interrupt control logic -- Maskable interrupts -- DMA support -- Programmable clock-rate generator -- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity -- Up to 2 stop bits in 1/16 increments -- Error-detection capabilities -- Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines -- Transmit and receive FIFO buffers I2C Module -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads -- Fully compatible with industry-standard I2C bus -- Master or slave modes support multiple masters -- Automatic interrupt generation with programmable level Queued Serial Peripheral Interface (QSPI) -- Full-duplex, three-wire synchronous transfer -- Up to four chip selects available -- Master operation -- Programmable master bit rates -- Up to 16 preprogrammed transfers Four 32-bit Timers with DMA request capability Pulse width modulation (PWM) unit -- Four identical channels Software Watchdog Timer
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Features
*
* *
*
*
*
-- 16-bit counter -- Low power mode support Phase Locked Loop (PLL) -- Reference crystal 8 to 25 MHz -- Low power modes supported -- Separate CLKOUT and DDR_CLKOUT signals Four Programmable Interrupt Timers (PITs) Interrupt Controllers (x2) -- Support for 58 independent interrupt sources, organized as follows: - 51 fully-programmable interrupt sources - 7 fixed-level external interrupt sources -- Unique vector number for each interrupt source -- Ability to mask any individual interrupt source or all interrupt sources (global mask-all) -- Support for hardware and software interrupt acknowledge (IACK) cycles -- Combinatorial path to provide wake-up from low power modes DMA Controller -- Four fully programmable channels -- Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability -- Source/destination address pointers that can increment or remain constant -- 24-bit transfer counter per channel -- Auto-alignment transfers supported for efficient block movement -- Bursting and cycle steal support -- Two-bus-clock internal access -- External request pins for each channel External Memory Interface -- External glueless connections to 8-, 16-, and 32-bit external memory devices (e.g., SRAM, flash, ROM, etc.) -- Glueless interface to SRAM devices with or without byte strobe inputs -- Programmable wait state generator -- 16-bit external bidirectional data bus -- 24-bit address bus -- Eight chip selects -- Byte/write enables -- Ability to boot from external memories that are 8 or 16 bits wide DDR SDRAM controller
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Features
*
*
*
*
-- Supports 16-bit wide memory devices -- Supports Dual Data Rate (DDR) SDRAM. -- Page mode support -- Programmable refresh interval timer. -- Sleep mode and self-refresh. -- Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer. -- Memory sizes from 8 Mbyte to 128 MByte (per chip select) -- 166 MHz data transfer rate (DDR) -- Two independent chip selects Reset -- Separate Reset In and Reset Out signals -- Six sources of reset (POR, External, Software, Watchdog, Loss of clock/lock) -- Status flag indication of source of last reset Chip Configurations -- System configuration during reset -- Bus Monitor, Abort Monitor -- Configurable output pad drive strength -- Unique Part Identification and Part Revision Numbers General Purpose I/O interface -- Up to 69 bits of general purpose I/O -- Coherent 32-bit control -- Bit manipulation supported via set/clear functions -- Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing -- Unique JTAG Part Identification and Part Revision Numbers
3.2
V2 Core Overview
The ColdFire V2 core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the V2 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations,
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Features
with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands as well as a complete set of instructions to process these data types. The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
3.3
Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Motorola's 683xx family of parts. The on-chip breakpoint resources include a total of 6 programmable registers--a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor's supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU's clock rate.
3.4
JTAG
The MCF5275 microprocessors support circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 326-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device's pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The MCF5275 implementation can do the following: * Perform boundary-scan operations to test circuit board electrical continuity * Sample MCF5275 system pins during operation and transparently shift out the result in the boundary scan register * Bypass the MCF5275 for a given circuit board test by effectively reducing the boundary-scan register to a single bit * Disable the output drive to pins during circuit-board testing * Drive output pins to stable levels
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 9
Features
3.5
On-chip Memories
The 64 Kbyte data RAM and the 16 Kbyte cache RAM for the processors are built using a RAM compiler. Both RAM blocks connect directly to the RAM controller via a standard single-port synchronous SRAM interface.
3.5.1
Cache
The 16-Kbyte cache can be configured into one of three possible organizations: a 16-Kbyte instruction cache, a 16-Kbyte data cache or a split 8-Kbyte instruction/8-Kbyte data cache. The configuration is software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory.
3.5.2
SRAM
The SRAM module provides a general-purpose 64-Kbyte memory implemented as four 16-Kbyte blocks that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FECs. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an example, system performance can be increased significantly if Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing.
3.6
Power Management
The MCF5275 family incorporates several low power modes of operation which are entered under program control and exited by several external trigger events. An integrated Power-On Reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises.
3.7
Fast Ethernet Controller (FEC)
The MCF5275 family contains up to two 10/100 BaseT fast Ethernet Controllers (FECs). Refer to Table 1 for device configurations. Each FEC includes these distinctive features: * IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition) * Built-in FIFO and DMA controller * Support for different Ethernet physical interfaces: -- 100Mbps IEEE 802.3 MII -- 10Mbps IEEE 802.3 MII
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 10 Preliminary Freescale Semiconductor
Features
* * * * * * *
* *
Support for full-duplex operation (200Mbps throughput) with a minimum system clock of 50MHz Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25MHz IEEE 802.3 full duplex flow control Programmable max frame length supports IEEE 802.1 VLAN tags and priority Retransmission from transmit FIFO following a collision (no system bus utilization) Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no system bus utilization) Address recognition -- Frames with broadcast address may be always accepted or always rejected -- Exact match for single 48-bit individual (unicast) address -- Hash (64-bit hash) check of individual (unicast) addresses -- Hash (64-bit hash) check of group (multicast) addresses -- Promiscuous mode RMON and IEEE statistics Interrupts for network activity and error conditions
3.8
Universal Serial Bus (USB)
The USB controller supports device mode data communications with a USB host (typically a PC). The programmable USB registers allow the user to enable or disable the module, control characteristics of individual endpoints, and monitor traffic flow through the module without ever seeing the low-level details of the USB protocol. The USB module provides the following features to the user: * Supports full-speed 12-Mbps USB devices and low-speed 1.5-Mbps devices * Full compliance with the Universal Serial Bus Specification, Revision 2.0 * Automatic hardware processing of USB standard device requests * USB device controller with protocol control and administration for up to eight endpoints, 16 interfaces, and 16 configurations. Endpoint types are programmable with support for up to eight control, interrupt, bulk, or isochronous endpoints * Independent interrupts for each endpoint * Supports remote wakeup via a register bit * Detects start-of-frame and missed start-of-frame for isochronous endpoint synchronization * Notification of start-of-frame, reset, suspend, and resume events
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 11
Features
3.9
Cryptography
Some of the MCF5275 family devices incorporate small, fast, and dedicated hardware accelerators for random number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions. This allows for the implementation of common Internet security protocol cryptography operations with performance well in excess of software-only algorithms. Refer to Table 1 for device configurations.
3.10 UARTs
The MCF5275 family of microprocessors each contain three (3) UARTs that function independently. Any of the three UARTs can be clocked by the system bus clock, eliminating the need for an external crystal. Each UART module contains the following major functional features: * Serial communication channel * 16-bit divider for clock generation * Internal channel control logic * Interrupt control logic * Maskable interrupts * DMA support * Programmable clock-rate generator * Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity * Up to 2 stop bits in 1/16 increments * Error-detection capabilities * Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines * Transmit and receive FIFO buffers * UART Modes of Operation: -- Full-duplex -- Auto-echo loopback -- Local loopback -- Remote loopback
3.11 I2C Bus
The I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C allows additional devices to be connected to the bus for expansion and system development. The I2C includes these distinctive features: * Compatibility with I2C bus standard
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 12 Preliminary Freescale Semiconductor
Features
* * * * * * * * * * *
Multiple-master operation Software programmable for one of 64 different serial clock frequencies Software selectable acknowledge bit Interrupt driven, byte-by-byte data transfer Arbitration lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Start and stop signal generation/detection Repeated START signal generation Acknowledge bit generation/detection Bus-busy detection DMA support
3.12 QSPI
The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to enqueue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers. The QSPI contains the following features: * Programmable queue to support up to 16 transfers without user intervention * Supports transfer sizes of 8 to 16 bits in 1-bit increments * Four peripheral chip-select lines * Baud rates from 162.1 Kbps to 20.75 Mbps at 83 MHz * Programmable delays before and after transfers * Programmable clock phase and polarity * Supports wraparound mode for continuous transfers
3.13 DMA Timers (DTIM0-DTIM3)
There are four independent, general purpose 32-bit platform timers (DTIM0, DTIM1, DTIM2, DTIM3) on the MCF5275 family of microprocessors. The output of an 8-bit prescaler clocks each timer. Each of the platform timer modules has these distinctive features: * Programmable sources for the clock input, including external clock * Input capture capability with programmable trigger edge on input pin * Output compare with programmable mode for the output pin * * * Free run and restart modes Maskable interrupts on input capture or reference compare DMA support
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 13
Features
Each of the four timer modules has four operating modes: * Capture mode * Output mode * Reference compare mode
3.14 Pulse Width Modulation (PWM) Module
The Pulse Width Modulation (PWM) module generates a synchronous series of pulses having programmable duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter. The PWM module has six channels with independent control of left and center aligned outputs on each channel. The MCF5275 family uses four of these channels namely 0, 1, 2 and 3. The emergency shutdown functionality (channel 5 only) is not used for the MCF5275 family. Each of the PWM channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs Summary of the main features include: * Independent PWM channels with programmable period and duty cycle * Dedicated counter for each PWM channel * Programmable PWM enable/disable for each channel * Software selection of PWM duty pulse polarity for each channel * Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled. * Programmable center or left aligned outputs on individual channels * 16-bit PWM resolution available by concatenating 8-bit channels * Four clock sources (A, B, SA and SB) provide for a wide range of frequencies. * Programmable Clock Select Logic
3.15 Software Watchdog Timer (WDT)
The watchdog timer is a 16-bit timer for helping software recover from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
3.16 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), frequency modulated phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 14 Preliminary Freescale Semiconductor
Features
the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.
3.17 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers which support 58 interrupt sources on the MCF5275. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 51 of the 58 sources of a given controller provide a programmable level [1-7] and priority within the level.
3.18 Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMA) Module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels that allow byte, word, or longword operand transfers. These transfers can be single or dual address to off-chip devices or dual address to on-chip devices. The DMA contains the following features: * Four fully independent, programmable DMA controller channels/bus modules * Auto-alignment feature for source or destination accesses * Single- and dual-address transfers * Up to four external request pins (DREQ[3:0]) * Channel arbitration on transfer boundaries * Data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer * Supports continuous-mode and cycle-steal transfers * Independent transfer widths for source and destination * Independent source and destination address registers * Provide two clock data transfers
3.19 External Interface Module (EIM)
The external interface module on MCF5275 devices handles the transfer of information between the internal core and memory, peripherals, or other processing elements in the external address space. Programmable chip select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a multiple of the block size. Each chip select is general purpose; however, any one of the chip selects can be programmed to provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 15
Features
The key features of the EIM are summarized below: * Eight independent, user-programmable chip-select signals (CS[7:0]) that interface with various memory types and peripherals * Address masking for 64 Kbyte to 4 gigabyte memory block sizes * Programmable wait states and port sizes * External master access to chip selects
3.20 Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller
The SDRAMC provides a 16-bit glueless external interface to double-data-rate (DDR) SDRAM memory devices. It is responsible for providing address, data and control signals for up to two independent chip-selects. The SDRAMC includes the following features: * Supports a glueless interface to DDR SDRAMs * 16-bit fixed memory port width * 32-bit data bus interface to Coldfire core * 16 bytes (8 beat x 16-bit) critical word first burst transfer * Up to 14 row address lines, up to 12 column address lines, maximum of two chip selects. The maximum row bits plus column bits is 24. * Supported SDRAM devices include: 8, 16, 32, 64, and 128Mbyte per chip select * Minimum memory configuration of 8 Mbyte--12 bit row address (RA), 8 bit column address (CA), 2 bit bank address (BA) and one chip select * Supports page mode to maximize the data rate * Supports sleep mode and self-refresh mode * Error detect and parity check are not supported
3.21 Resets
The Reset Controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset. The MCF5275 family has six (6) sources of reset: * External * Power On Reset (POR) * Watchdog timer * * * PLL Loss of Lock PLL Loss of Clock Software
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Signal Descriptions
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset.
3.22 General Purpose I/O
Most peripheral I/O pins on MCF5275 devices are muxed with GPIO, adding flexibility and usability to all signals on the chip.
4
Signal Descriptions
NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. Signal Information and Muxing
Bonded on MCF5274L/5L 196 MAPBGA 1 1 1 1 1 2 1 3 Bonded on MCF5274/75 256 MAPBGA 1 1 1 1 1 2 1 3
Table 2 lists the signals for the MCF5275 in functional group order.
Name
GPIO Port
Alternate1
Alternate2 Dir.1
Reset RESET RSTOUT -- -- -- -- Clock EXTAL XTAL CLKOUT -- -- -- -- -- -- Mode Selection CLKMOD[1:0] RCON -- -- -- -- -- -- I I -- -- -- I O O -- -- I O
External Memory Interface and Ports A[23:21] PADDR[7:5] CS[6:4] -- O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 17
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
Bonded on MCF5274L/5L 196 MAPBGA 21 16 2 1 1 0 1 1 1 1 0 7 1 1 1 2 1 1 1 1 2 1 2 3 1 2 1 Freescale Semiconductor Bonded on MCF5274/75 256 MAPBGA 21 16 2 1 1 1 1 1 1 1 1 7 1 1 1 2 1 1 1 1 2 1 2 3 1 2 1
Name
GPIO Port
Alternate1
Alternate2 Dir.1
A[20:0] D[31:16] BS[3:2] OE TA TEA R/W TSIZ1 TSIZ0 TS TIP
-- -- PBS[3:2] PBUSCTL[7] PBUSCTL[6] PBUSCTL[5] PBUSCTL[4] PBUSCTL[3] PBUSCTL[2] PBUSCTL[1] PBUSCTL[0]
-- -- CAS[3:2] -- -- DREQ1 -- DACK1 DACK0 DACK2 DREQ0 Chip Selects
-- -- -- -- -- -- -- -- -- -- --
O O O O I I O O O O O
CS[7:1] CS0
PCS[7:1] --
-- --
-- --
O O
DDR SDRAM Controller DDR_CLKOUT DDR_CLKOUT SD_CS[1:0] SD_SRAS SD_SCAS SD_WE SD_A10 SD_DQS[1:0] SD_CKE SD_VREF -- -- PSDRAM[7:6] PSDRAM[5] PSDRAM[4] PSDRAM[3] -- PSDRAM[1:0] PSDRAM[2] -- -- -- CS[3:2] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O O O O O O I/O O I
External Interrupts Port IRQ[7:5] IRQ[4] IRQ[3:2] IRQ1 PIRQ[7:5] PIRQ[4] PIRQ[3:2] PIRQ[1] -- DREQ2 DREQ[3:2] -- -- -- -- -- I I I I
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 18 Preliminary
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
Bonded on MCF5274L/5L 196 MAPBGA 1 1 1 1 1 1 1 1 1 1 3 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bonded on MCF5274/75 256 MAPBGA 1 1 1 1 1 1 1 1 1 1 3 1 3 1 1 1 1 1 1 1 1 1 1 1 3 1 3 1
Name
GPIO Port
Alternate1
Alternate2 Dir.1
FEC0 FEC0_MDIO FEC0_MDC FEC0_TXCLK FEC0_TXEN FEC0_TXD[0] FEC0_COL FEC0_RXCLK FEC0_RXDV FEC0_RXD[0] FEC0_CRS FEC0_TXD[3:1] FEC0_TXER FEC0_RXD[3:1] FEC0_RXER PFECI2C[5] PFECI2C[4] PFEC0H[7] PFEC0H[6] PFEC0H[5] PFEC0H[4] PFEC0H[3] PFEC0H[2] PFEC0H[1] PFEC0H[0] PFEC0L[7:5] PFEC0L[4] PFEC0L[3:1] PFEC0L[0] I2C_SDA I2C_SCL -- -- -- -- -- -- -- -- -- -- -- -- FEC1 FEC1_MDIO FEC1_MDC FEC1_TXCLK FEC1_TXEN FEC1_TXD[0] FEC1_COL FEC1_RXCLK FEC1_RXDV FEC1_RXD[0] FEC1_CRS FEC1_TXD[3:1] FEC1_TXER FEC1_RXD[3:1] FEC1_RXER PFECI2C[3] PFECI2C[2] PFEC1H[7] PFEC1H[6] PFEC1H[5] PFEC1H[4] PFEC1H[3] PFEC1H[2] PFEC1H[1] PFEC1H[0] PFEC1L[7:5] PFEC1L[4] PFEC1L[3:1] PFEC1L[0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O I I O I I I I I O O I O U2RXD U2TXD -- -- -- -- -- -- -- -- -- -- -- -- I/O O I I O I I I I I O O I O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 19
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
Bonded on MCF5274L/5L 196 MAPBGA 1 1 -- 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 Freescale Semiconductor Bonded on MCF5274/75 256 MAPBGA 1 1 -- 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Name
GPIO Port
Alternate1
Alternate2 Dir.1
I2C I2C_SDA I2C_SCL PFECI2C[1] PFECI2C[0] U2RXD U2TXD DMA DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for DREQ2, TEA for DREQ1, and TIP for DREQ0. QSPI QSPI_CS[3:2] QSPI_CS1 QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT PQSPI[6:5] PQSPI[4] PQSPI[3] PQSPI[2] PQSPI[1] PQSPI[0] PWM[3:2] SD_CKE -- I2C_SCL I2C_SDA -- UARTs U0CTS U0RTS U0RXD U0TXD U1CTS U1RTS U1RXD U1TXD U2CTS U2RTS U2RXD U2TXD PUARTL[0] PUARTL[1] PUARTL[3] PUARTL[2] PUARTL[4] PUARTL[5] PUARTL[7] PUARTL[6] PUARTH[1] PUARTH[0] PUARTH[3] PUARTH[2] -- -- -- -- -- -- -- -- PWM1 PWM0 -- -- USB USB_SPEED PUSBH[0] -- -- I/O -- -- -- -- -- -- -- -- -- -- -- -- I O I O I O I O I O I O DACK[3:2] -- -- -- -- -- O O O O I O -- -- I/O I/O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 20 Preliminary
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
Bonded on MCF5274L/5L 196 MAPBGA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 1 1 Bonded on MCF5274/75 256 MAPBGA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 1 1
Name
GPIO Port
Alternate1
Alternate2 Dir.1
USB_CLK USB_RN USB_RP USB_RXD USB_SUSP USB_TN USB_TP USB_TXEN
PUSBL[7] PUSBL[6] PUSBL[5] PUSBL[4] PUSBL[3] PUSBL[2] PUSBL[1] PUSBL[0]
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
I I I I O O O O
Timers (and PWMs) DT3IN DT3OUT DT2IN DT2OUT DT1IN DT1OUT DT0IN DT0OUT PTIMER[7] PTIMER[6] PTIMER[5] PTIMER[4] PTIMER[3] PTIMER[2] PTIMER[1] PTIMER[0] DT3OUT PWM3 DT2OUT PWM2 DT1OUT PWM1 DT0OUT PWM0 BDM/JTAG2 DSCLK PSTCLK BKPT DSI DSO JTAG_EN DDATA[3:0] PST[3:0] -- -- -- -- -- -- -- -- TRST TCLK TMS TDI TDO -- -- -- Test TEST PLL_TEST -- -- -- -- Power Supplies -- -- I I -- -- -- -- -- -- -- -- I O I I O I O O U2RTS U2CTS -- -- -- -- -- -- I O I O I O I O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 21
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
Bonded on MCF5274L/5L 196 MAPBGA 1 1 Bonded on MCF5274/75 256 MAPBGA 1 1
Name
GPIO Port
Alternate1
Alternate2 Dir.1
VDDPLL VSSPLL VDD VSS OVDD OVSS SD_VDD
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
I I I I I I I
NOTES: 1 Refers to pin's primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
4.1
Reset Signals
Table 3. Reset Signals
Signal Name Abbreviation RESET RSTOUT Function Primary reset input to the device. Asserting RESET immediately resets the CPU and peripherals. Driven low for 128 CPU clocks when the soft reset bit of the system configuration register (SCR[SOFTRST]) is set. It is driven low for 32K CPU clocks when the software watchdog timer times out or when a low input level is applied to RESET. I/O I O
Table 3 describes signals that are used to either reset the chip or as a reset indication.
Reset In Reset Out
4.2
PLL and Clock Signals
Table 4 describes signals that are used to support the on-chip clock generation circuitry.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 22 Preliminary Freescale Semiconductor
Signal Descriptions
Table 4. PLL and Clock Signals
Signal Name External Clock In Abbreviation EXTAL Function Always driven by an external clock input except when used as a connection to the external crystal when the internal oscillator circuit is used. The clock source is configured during reset by CLKMOD[1:0]. Used as a connection to the external crystal when the internal oscillator circuit is used to drive the crystal. This output signal reflects the internal system clock. I/O I
Crystal Clock Out
XTAL CLKOUT
O O
4.3
Mode Selection
Table 5. Mode Selection Signals
Signal Name Abbreviation Function I/O I I
Table 5 describes signals used in mode selection.
Clock Mode Selection Reset Configuration
CLKMOD[1:0] Configure the clock mode after reset. RCON Indicates whether the external D[31:16] pin states affect chip configuration at reset.
4.4
External Memory Interface Signals
These signals are used for doing transactions on the external bus. Table 6 describes signals that are used for doing transactions on the external bus.
Table 6. External Memory Interface Signals
Signal Name Address Bus Abbreviation A[23:0] Function The 24 dedicated address signals define the address of external byte, word, and longword accesses. These three-state outputs are the 24 lsbs of the internal 32-bit address bus and multiplexed with the SDRAM controller row and column addresses. These three-state bidirectional signals provide the general purpose data path between the processor and all other devices. I/O O
Data Bus
D[31:16]
I/O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 23
Signal Descriptions
Table 6. External Memory Interface Signals (continued)
Signal Name Byte Strobes Abbreviation BS[3:2] Function Define the flow of data on the data bus. During SRAM and peripheral accesses, these output signals indicate that data is to be latched or driven onto a byte of the data when driven low. The BS[3:2] signals are asserted only to the memory bytes used during a read or write access. BS3 controls access to the most significant byte lane of data, and BS2 controls access to the least significant byte lane of data. The BS[3:2] signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM, or cache. During SDRAM accesses, these signals act as the CAS[3:2] signals, which indicate a byte transfers between SDRAM and the chip when driven high. For SRAM or Flash devices, the BS[3:2] outputs should be connected to individual byte strobe signals. For SDRAM devices, the BS[3:2] should be connected to individual SDRAM DQM signals. Note that most SDRAMs associate DQM1 with the MSB, in which case BS3 should be connected to the SDRAM's DQM1 input. Output Enable Transfer Acknowledge OE TA Indicates when an external device can drive data during external read cycles. Indicates that the external data transfer is complete. During a read cycle, when the processor recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the processor recognizes TA, the bus cycle is terminated. Indicates an error condition exists for the bus transfer. The bus cycle is terminated and the CPU begins execution of the access error exception. Indicates the direction of the data transfer on the bus for SRAM (R/W) and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device When the device is in normal mode, dynamic bus sizing lets the programmer change data bus width between 8, 16, and 32 bits for each chip select. The initial width for the bootstrap program chip select, CS0, is determined by the state of TSIZ[1:0]. The program should select bus widths for the other chip selects before accessing the associated memory space. These pins our output pins. Bus control output signal indicating the start of a transfer. Bus control output signal indicating bus transfer in progress. These output signals select external devices for external bus transactions. The CS[3:2] can also be configured to function as SDRAM chip selects SD_CS[1:0]. O I I/O O
Transfer Error Acknowledge Read/Write
TEA
I
R/W
O
Transfer Size
TSIZ[1:0]
O
Transfer Start Transfer in Progress Chip Selects
TS TIP CS[7:0]
O O O
4.5
DDR SDRAM Controller Signals
Table 7 describes signals that are used for DDR SDRAM accesses.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 24 Preliminary Freescale Semiconductor
Signal Descriptions
Table 7. SDRAM Controller Signals
Signal Name SDRAM Clock Out SDRAM Inverted Clock Out SDRAM Synchronous Row Address Strobe Abbreviation Function I/O O O O O O O O O O
DDR_CLKOUT This output signal reflects the internal system clock. DDR_CLKOUT This output signal reflects the inverted internal system clock. SD_SRAS SDRAM synchronous row address strobe. SDRAM synchronous column address strobe. SDRAM write enable. SDRAM address bit 10 or command. SDRAM chip select signals. SDRAM clock enable. SDRAM byte-lane read/write data strobe signals.
SDRAM Synchronous SD_SCAS Column Address Strobe SDRAM Write Enable SDRAM A10 SDRAM Chip Selects SDRAM Clock Enable SDRAM Data Strobes SD_WE SD_A10 SD_CS[1:0] SD_CKE SD_DQS[3:2]
4.6
External Interrupt Signals
Table 8. External Interrupt Signals
Signal Name Abbreviation IRQ[7:1] Function External interrupt sources. IRQ[3:2] can also be configured as DMA request signals DREQ[3:2]. IRQ4 can also be configured as DMA request signals DREQ2. I/O I
Table 8 describes the external interrupt signals.
External Interrupts
4.7
Fast Ethernet Controller Signals
Table 9. Ethernet Module (FEC) Signals
Signal Name Abbreviation FECn_MDIO Function Transfers control information between the external PHY and the media-access controller. Data is synchronous to FECn_MDC. Applies to MII mode operation. This signal is an input after reset. When the FEC is operated in 10Mbps 7-wire interface mode, this signal should be connected to VSS. In Ethernet mode, FECn_MDC is an output clock which provides a timing reference to the PHY for data transfers on the FECn_MDIO signal. Applies to MII mode operation. Input clock which provides a timing reference for FECn_TXEN, FECn_TXD[3:0] and FECn_TXER I/O I/O
The following signals are used by the Ethernet modules for data and clock signals.
Management Data
Management Data Clock Transmit Clock
FECn_MDC
O
FECn_TXCLK
I
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 25
Signal Descriptions
Table 9. Ethernet Module (FEC) Signals (continued)
Signal Name Transmit Enable Abbreviation FECn_TXEN Function Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first FECn_TXCLK following the final nibble of the frame. FECn_TXD0 is the serial output Ethernet data and is only valid during the assertion of FECn_TXEN. This signal is used for 10-Mbps Ethernet data. It is also used for MII mode data in conjunction with FECn_TXD[3:1]. Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. Provides a timing reference for FECn_RXDV, FECn_RXD[3:0], and FECn_RXER. Asserting the receive data valid (FECn_RXDV) input indicates that the PHY has valid nibbles present on the MII. FECn_RXDV should remain asserted from the first recovered nibble of the frame through to the last nibble. Assertion of FECn_RXDV must start no later than the SFD and exclude any EOF. FECn_RXD0 is the Ethernet input data transferred from the PHY to the media-access controller when FECn_RxDV is asserted. This signal is used for 10-Mbps Ethernet data. This signal is also used for MII mode Ethernet data in conjunction with FECn_RXD[3:1]. When asserted, indicates that transmit or receive medium is not idle. Applies to MII mode operation. I/O O
Transmit Data 0
FECn_TXD0
O
Collision Receive Clock Receive Data Valid
FECn_COL FECn_RXCLK FECn_RXDV
I I I
Receive Data 0
FECn_RXD0
I
Carrier Receive Sense FECn_CRS Transmit Data 1-3 Transmit Error
I O O
FECn_TXD[3:1] In Ethernet mode, these pins contain the serial output Ethernet data and are valid only during assertion of FECn_TXEN in MII mode. FECn_TXER In Ethernet mode, when FECn_TXER is asserted for one or more clock cycles while FECn_TXEN is also asserted, the PHY sends one or more illegal symbols. FECn_TXER has no effect at 10 Mbps or when FECn_TXEN is negated. Applies to MII mode operation.
Receive Data 1-3
FECn_RXD[3:1] In Ethernet mode, these pins contain the Ethernet input data transferred from the PHY to the Media Access Controller when FECn_RXDV is asserted in MII mode operation. FECn_RXER In Ethernet mode, FECn_RXER--when asserted with FECn_RXDV--indicates that the PHY has detected an error in the current frame. When FECn_RXDV is not asserted FECn_RXER has no effect. Applies to MII mode operation.
I
Receive Error
O
4.8
Queued Serial Peripheral Interface (QSPI)
Table 10 describes QSPI signals.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 26 Preliminary Freescale Semiconductor
Signal Descriptions
Table 10. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name QSPI Syncrhonous Serial Output QSPI Synchronous Serial Data Input QSPI Serial Clock Abbreviation QSPI_DOUT Function Provides the serial data from the QSPI and can be programmed to be driven on the rising or falling edge of QSPI_CLK. Each byte is sent msb first. Provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPI_CLK. Each byte is written to RAM lsb first. Provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable. The output frequency is programmed according to the following formula, in which n can be any value between 1 and 255: SPI_CLK = fsys/2 / n I/O O
QSPI_DIN
I
QSPI_CLK
O
Synchronous Peripheral QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be Chip Selects active high or low. QSPI_CS1 can also be configured as SDRAM clock enable signal SD_CKE.
O
4.9
I2C I/O SIGNALS
Table 11. I2C I/O Signals
Signal Name Abbreviation I2C_SCL Function Open-drain clock signal for the for the I2C interface. Either it is driven by the I2C module when the bus is in the master mode or it becomes the clock input when the I2C is in the slave mode. Open-drain signal that serves as the data input/output for the I2C interface. I/O I/O
Table 11 describes the I2C serial interface module signals.
Serial Clock
Serial Data
I2C_SDA
I/O
4.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not supported.
Table 12. UART Module Signals
Signal Name Transmit Serial Data Output Abbreviation UnTXD Function Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, lsb first, on this pin at the falling edge of the serial clock source. Receiver serial data inputs for the UART modules. Data received on this pin is sampled on the rising edge of the serial clock source lsb first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it. I/O O
Receive Serial Data Input
UnRXD
I
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 27
Signal Descriptions
Table 12. UART Module Signals (continued)
Signal Name Clear-to-Send Request-to-Send Abbreviation UnCTS UnRTS Function Indicate to the UART modules that they can begin data transmission. Automatic request-to-send outputs from the UART modules. UnRTS can also be configured to be asserted and negated as a function of the RxFIFO level. I/O I O
4.11 USB Signals
Table 13 describes the USB serial interface module signals.
Table 13. USB Module Signals
Signal Name USB Clock Abbreviation USB_CLK Function This 48MHz (or 6MHz) clock is used by the USB module for both clock recovery and generation of a 12Mhz (or 1.5MHz) internal bit clock. I/O I
USB Speed
USB_SPEED Applications which make use of low speed USB signalling must be able to switch the USB transceiver between low speed and full speed operations. Software has control of this function by driving the state of the USB_SPD bit in the USB_CTRL register onto the USB_SPEED pin. USB_RN This signal is one half of the differential USB signal, and is extracted from the USB cable via a single ended input buffer on the analog front end. This signal is used by the module for detecting the single ended 0 (SE0) USB bus state. This signal is one half of the differential USB signal, and is extracted from the USB cable via a single ended input buffer on the analog front end. This signal is used by the module for detecting the single ended 0 (SE0) USB bus state. Input data from the differential input receiver. USB_RXD is the single-ended data extracted from the USB_RP and USB_RN signals via a differential input buffer. After a long period of inactivity (3.0ms minimum), the USB will enter suspend mode, indicated on the interface by an active state on USB_SUSP. During this mode, the device is supposed to enter a low power state while waiting for a wake-up from the USB Host. When the device enters suspend mode, it asserts the suspend signal which forces the analog front end into a low power state. When the device leaves suspend mode, USB_SUSP is deasserted, enabling the analog front end for normal USB operations. This signal is one half of the differential NRZI formatted output from the USB module. It is fed to the transmitted D- input of the analog front end.
I/O
USB Received D-
I
USB Received D+
USB_RP
I
USB Receive Data
USB_RXD
I
USB Suspended
USB_SUSP
O
USB Transmitted D-
USB_TN
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 28 Preliminary Freescale Semiconductor
Signal Descriptions
Table 13. USB Module Signals (continued)
Signal Name USB Transmitted D+ Abbreviation USB_TP Function This signal is one half of the differential NRZI formatted output from the module. It is fed to the transmitted D+ input of the analog front end. This signal is an active low output enable for the differential drivers on the analog front end. When this signal is active, the differential drivers will drive the USB. When this signal is inactive, the differential drivers will tristate their outputs. I/O O
USB Transmit Enable
USB_TXEN
O
4.12 DMA Timer Signals
Table 14 describes the signals of the four DMA timer modules.
Table 14. DMA Timer Signals
Signal Name DMA Timer 0 Input Abbreviation DT0IN Function Can be programmed to cause events to occur in first platform timer. It can either clock the event counter or provide a trigger to the timer value capture logic. The output from first platform timer. Can be programmed to cause events to occur in the second platform timer. This can either clock the event counter or provide a trigger to the timer value capture logic. The output from the second platform timer. Can be programmed to cause events to occur in the third platform timer. It can either clock the event counter or provide a trigger to the timer value capture logic. The output from the third platform timer. Can be programmed as an input that causes events to occur in the fourth platform timer. This can either clock the event counter or provide a trigger to the timer value capture logic. The output from the fourth platform timer. I/O I
DMA Timer 0 Output DMA Timer 1 Input
DT0OUT DT1IN
O I
DMA Timer 1 Output DMA Timer 2 Input
DT1OUT DT2IN
O I
DMA Timer 2 Output DMA Timer 3 Input
DT2OUT DT3IN
I I
DMA Timer 3 Output
DT3OUT
O
4.13 Pulse Width Modulator Signals
Table 15 describes the PWM signals. Note that the primary functions of these pins are DMA Timer outputs (DTnOUT).
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 29
Signal Descriptions
Table 15. PWM Signals
Signal Name Abbreviation Function Pulse width modulated output for PWM channel 0. Pulse width modulated output for PWM channel 1. Pulse width modulated output for PWM channel 2. Pulse width modulated output for PWM channel 3. I/O O O O O
PWM Output Channel 0 PWM0 PWM Output Channel 1 PWM1 PWM Output Channel 2 PWM2 PWM Output Channel 3 PWM3
4.14 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM logic.
Table 16. Debug Support Signals
Signal Name Test Reset Test Clock Test Mode Select Test Data Input Test Data Output Abbreviation TRST TCLK TMS TDI TDO Function This active-low signal is used to initialize the JTAG logic asynchronously. Used to synchronize the JTAG logic. Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK. Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK. Serial output for test instructions and data. TDO is three-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK. Clocks the serial communication port to the BDM module during packet transfers. Used to request a manual breakpoint. This internally-synchronized signal provides data input for the serial communication port to the BDM module. This internally-registered signal provides serial output communication for BDM module responses. Display captured processor data and breakpoint status. The CLKOUT signal can be used by the development system to know when to sample DDATA[3:0]. Indicate core status, as shown in Table 17. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0]. I/O I I I I O
Development Serial Clock Breakpoint Development Serial Input Development Serial Output Debug Data
DSCLK BKPT DSI DSO DDATA[3:0]
I I I O O
Processor Status Outputs
PST[3:0]
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 30 Preliminary Freescale Semiconductor
Signal Descriptions
Table 17. Processor Status
PST[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Processor Status Continue execution Begin execution of one instruction Reserved Entry into user mode Begin execution of PULSE and WDDATA instructions Begin execution of taken branch Reserved Begin execution of RTE instruction Begin one-byte transfer on DDATA Begin two-byte transfer on DDATA Begin three-byte transfer on DDATA Begin four-byte transfer on DDATA Exception processing Reserved Processor is stopped Processor is halted
4.15 Test Signals
Table 18 describes test signals.
Table 18. Test Signals
Signal Name Test Abbreviation TEST Function Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. Reserved for factory testing only and should be treated as a no-connect (NC). I/O I
PLL Test
PLL_TEST
I
4.16 Power and Ground Pins
The pins described in Table 19 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 31
Chip Configuration
Table 19. Power and Ground Pins
Signal Name PLL Analog Supply Abbreviation VDDPLL, VSSPLL VDDO VDD VSS Function Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply. These pins supply positive power to the I/O pads. These pins supply positive power to the core logic. This pin is the negative supply (ground) to the chip. I/O I
Positive Supply Positive Supply Ground
I I
5
5.1
* *
Chip Configuration
Device Operating Options
Chip operating mode: -- Master mode Boot device/size: -- External device boot - 32-bit - 16-bit (Default) - 8-bit Output pad strength: -- Partial drive strength (Default) -- Full drive strength Clock mode: -- Normal PLL with external crystal -- Normal PLL with external clock -- 1:1 PLL Mode -- External oscillator mode (no PLL) Chip Select Configuration: -- PADDR[7:5] configured as chip select(s) and/or address line(s) - PADDR[7:5] configured as A23-A21 (default) - PADDR configured as CS6, PADDR[6:5] as A22-A21 - PADDR[7:6] configured as CS[6:5], PADDR5 as A21 - PADDR[7:5] configured as CS[6:4]
*
*
*
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 32 Preliminary Freescale Semiconductor
Chip Configuration
5.2
Chip Configuration Pins
Table 20. Configuration Pin Descriptions
Pin RCON Chip Configuration Function Chip configuration enable Select chip operating mode Pin State/Meaning 1 disabled 0 enabled 111 110 101 100 0xx master reserved reserved reserved reserved Value read defaults to 32-bit Comments Active low: if asserted, then all configuration pins must be driven appropriately for desired operation
D26, D17, D16
D19, D18
Select external boot device data port size Select output pad drive strength Select clock mode
00,11 external (32-bit) 10 external (8-bit) 01 external (16-bit) 1 Full 0 Partial
D21 CLKMOD1, CLKMOD0
00 External clock mode (no VDDPLL must be supplied if a PLL PLL) mode is selected 01 1:1 PLL mode 10 Normal PLL with external clock reference 11 Normal PLL with crystal clock reference 00 PADDR[7:5] configured as A23-A21 (default) 10 PADDR7 configured as CS6, PADDR[6:5] as A22-A21 01 PADDR[7:6] configured as CS[6:5], PADDR5 as A21 11 PADDR[7:5] configured as CS[6:4] 0 BDM mode 1 JTAG mode
D25, D24
Select chip select / address line
JTAG_EN
Selects BDM or JTAG mode
5.3
Chip Configuration Circuit
Figure 2 shows a block diagram of the recommended circuit used to drive the reset configuration values for the MCF5275.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 33
Design Recommendations
74HC244 D16 Inputs driven high or low as needed D17 D18 D19 D21 D24 D25 D26 OE
MCF5275
RSTOUT
RCON VDD/VSS CLKMOD0 CLKMOD1 JTAG_EN
Figure 2. MCF5275 Recommended Reset Configuration Circuit
6
6.1
* * *
Design Recommendations
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5275. See application note AN1259 System Design and Layout Techniques for Noise Reduction in MCU-Based Systems. Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing.
6.2
*
Power Supply
33uF, 0.1uF and 0.01uF across each power supply
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 34 Preliminary Freescale Semiconductor
Design Recommendations
6.3
* *
Decoupling
Place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint of the package. 0.1uF and 0.01uF at each supply input
6.4
*
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See electricals.
6.5
*
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
6.6
* * * * * * * *
Clocking Recommendations
Use a multi-layer board with a separate ground plane. Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. Do not run a high frequency trace around crystal circuit. Ensure that the ground for the bypass capacitors is connected to a solid ground trace. Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. Tie the ground pin to the most solid ground in the system. Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. Tie XTAL to ground when an external oscillator is clocking the device.
6.7
6.7.1
6.7.1.1
Interface Recommendations
DDR SDRAM Controller
SDRAM Controller Signals in Synchronous Mode
Table 21 shows the behavior of SDRAM signals in synchronous mode.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 35
Design Recommendations
Table 21. Synchronous DRAM Signal Connections
Signal SD_SRAS Description Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller's SDRAM_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAM read/write. Asserted for write operations and negated for read operations. Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals. Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. Bus clock output. Connects to the CLK input of SDRAMs.
SD_SCAS
SD_WE SD_CS[1:0] SD_CKE
BS[3:2] DDR_CLKOUT
6.7.1.2
Address Multiplexing
Table 22 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table.
Table 22. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address 17 16 15 14 13 12 11 10 9 17 18 19 20 21 17 16 15 14 13 12 11 10 9 17 18 19 20 21 0 1 2 3 4 5 6 7 8 16 17 18 19 20 32-bit port only 16-bit port only or 32-bit port with only 8 column address lines 16-bit port only when at least 9 column address lines are used Notes Related to Port Sizes 8-bit port only 8- and 16-bit ports only
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 36 Preliminary Freescale Semiconductor
Design Recommendations
Table 22. Generic Address Multiplexing Scheme (continued)
Address Pin Row Address Column Address 22 23 24 25 22 23 24 25 21 22 23 24 Notes Related to Port Sizes
The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF5275 to SDRAM. To use the tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5275, which is not necessarily the SDRAM port size. For example, if two 8M x 8-bit SDRAMs together form a 8M x 16-bit memory, the port size is 16 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.
Table 23. MCF5275 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 24. MCF5275 to SDRAM Interface (8-Bit Port,10-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 25. MCF5275 to SDRAM Interface (8-Bit Port,11-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 37
Design Recommendations
Table 26. MCF5275 to SDRAM Interface (8-Bit Port,12-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 23 22 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 27. MCF5275 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 23 22 25 24 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 28. MCF5275 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 29. MCF5275 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 30. MCF5275 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 9 8 A7 18 17 A8 20 19 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 21 22 23 24 25 26 27 28 29 30 31
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 38 Preliminary Freescale Semiconductor
Design Recommendations
Table 31. MCF5275 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 9 8 A7 18 17 A8 20 19 22 21 23 24 25 26 27 28 29 30 31
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 32. MCF5275 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 A9 9 8 A7 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 18 17 A8 20 19 A9 22 21 24 23 25 26 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 33. MCF5275 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 A9 9 8 A7 A18 A20 A22 A24 A26 A27 A28 A29 A30 A31 18 17 A8 20 19 A9 22 21 24 23 26 25 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17
Table 34. MCF5275 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 14 3 13 4 12 5 11 6 10 7 9 8 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 35. MCF5275 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 9 8 A6 17 16 A7 19 18 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 20 21 22 23 24 25 26 27 28 29 30 31
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 39
Design Recommendations
Table 36. MCF5275 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 9 8 A6 17 16 A7 19 18 A8 21 20 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 22 23 24 25 26 27 28 29 30 31
Table 37. MCF5275 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 A9 9 8 A6 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 17 16 A7 19 18 A8 21 20 A9 23 22 A10 A11 A12 A13 A14 A15 A16 A17 A18 24 25 26 27 28 29 30 31
Table 38. MCF5275 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 A9 9 8 A6 A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 17 16 A7 19 18 A8 21 20 A9 23 22 25 24 26 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17
6.7.1.2.1
SDRAM Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the MCF5275, the connections would be as shown in Table 39.
Table 39. SDRAM Hardware Connections
SDRAM Pins MCF5275 Pins A0 A15 A1 A14 A2 A13 A3 A12 A4 A11 A5 A10 A6 A9 A7 A17 A8 A18 A9 A19 A10 = CMD A20 BA0 A21 BA1 A22
6.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 40.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 40 Preliminary Freescale Semiconductor
Design Recommendations
Table 40. MII Mode
Signal Description Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data Receive error Management channel clock Management channel serial data MCF5275 Pin FECn_TXCLK FECn_TXEN FECn_TXD[3:0] FECn_TXER FECn_COL FECn_CRS FECn_RXCLK FECn_RXDV FECn_RXD[3:0] FECn_RXER FECn_MDC FECn_MDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275 configuration for seven-wire serial mode connections to the external transceiver are shown in Table 41.
Table 41. Seven-Wire Mode Configuration
Signal Description Transmit clock Transmit enable Transmit data Collision Receive clock Receive enable Receive data Unused, configure as PB14 Unused input, tie to ground Unused, configure as PB[13:11] Unused output, ignore Unused, configure as PB[10:8] Unused, configure as PB15 Input after reset, connect to ground MCF5275 Pin FECn_TXCLK FECn_TXEN FECn_TXD[0] FECn_COL FECn_RXCLK FECn_RXDV FECn_RXD[0] FECn_RXER FECn_CRS FECn_RXD[3:1] FECn_TXER FECn_TXD[3:1] FECn_MDC FECn_MDIO
Refer to the M5275EVBevaluation board user's manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5275 site by navigating from: http://e-www.motorola.com/ following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5275 and M5275EVB links.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 41
Pinout
6.7.3
BDM
Use the BDM interface as shown in the M5275EVB evaluation board user's manual. The schematics for this board are accessible at the MCF5275 site by navigating from: http://e-www.motorola.com/ following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5275 and M5275EVB links.
7
7.1
Pinout
256 MAPBGA Pinout
Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 42 Preliminary Freescale Semiconductor
Pinout
1 A VSS FEC1_ RXD3 FEC1_ TXCLK FEC1_ TXER FEC1_ TXD3 FEC1_ TXD0 FEC1_ MDIO DT1IN 2 FEC1_ RXD1 FEC1_ RXD2 FEC1_ RXER FEC1_ TXEN FEC1_ TXD2 FEC1_ TXD1 FEC1_ MDC DT1OUT 3 FEC1_ RXDV FEC1_ RXD0 FEC0_ TXCLK FEC0_ TXER FEC0_ TXD3 FEC0_ TXD2 DT0OUT 4 FEC1_ CRS FEC1_ RXCLK FEC0_ RXER FEC0_ TXEN NC FEC0_ TXD1 FEC0_ TXD0 NC 5 FEC1_ COL FEC0_ RXDV FEC0_ RXD2 FEC0_ RXD3 VSS 6 FEC0_ COL FEC0_ RXCLK FEC0_ RXD0 FEC0_ RXD1 OVDD 7 FEC0_ MDIO FEC0_ MDC FEC0_ CRS U0RTS 8 U0RXD 9 U1RXD 10 VSS I2C_ SDA I2C_ SCL CS7 11 A23 12 A20 13 A17 14 A14 15 SD_ VREF A11 16 VSS A
B
U0TXD
U1TXD
A22
A19
A16
A13
A9
B
C
U0CTS
U1CTS
A21
A18
A15
A12
A10
A8
C
D
VDD
U1RTS
CS6
CS5
CS4
A7
A6
TSIZ1
D
E
OVDD
OVDD SD_VDD SD_VDD SD_VDD
VSS
CS3
A5
A4
A3
E
F
OVDD
VSS
OVDD
OVDD SD_VDD SD_VDD
VSS
SD_VDD
CS2
A2 USB_ SPEED IRQ4
A1 USB_ CLK IRQ5
A0
F
G
OVDD
OVDD
VSS
VSS
VSS
VSS
SD_VDD SD_VDD
IRQ7
TSIZ0
G
H
DT0IN
OVDD
OVDD
VSS
VSS
VSS
VSS
SD_VDD SD_VDD
VDD
IRQ6
H
J
VSS
DT2IN
DT2OUT
DT3IN
SD_VDD
SD_VDD
VSS
VSS
VSS
VSS
OVDD
OVDD
IRQ2
IRQ3
USB_RP USB_RN J
K
OE SD_ SCAS D31
SD_WE SD_ SRAS SD_CS1
DT3OUT
VDD
SD_VDD
SD_VDD
VSS
VSS
VSS
VSS
OVDD
OVDD
IRQ1
USB_TN USB_TP VSSPLL K USB_ TXEN PLL_ TEST USB_ RXD VDDPLL
L
SD_CKE
TS
SD_VDD
VSS
SD_VDD SD_VDD OVDD
OVDD
VSS
OVDD
TA USB_ SUSP CLK MOD1 CLK MOD0 QSPI_ CS3 QSPI_ DIN 13
EXTAL
L
M
BS3
SD_DQS3
VSS
SD_VDD
SD_VDD SD_VDD OVDD
OVDD
OVDD
NC QSPI_ CS2 QSPI_ CS0 QSPI_ DOUT CLKOUT 12
XTAL
M
N
D30
D29
D28
D20
D16
SD_A10
CS1
VDD
TEST
DDATA2 DDATA0
RSTOUT RESET TRST/ DSCLK JTAG_ EN QSPI_ CS1 14 TDO/ DSO TMS/ BKPT QSPI_ CLK 15
VSS
N
P
D27
D26
D23
D19
SD_DQS2
TIP
R/W
RCON
U2CTS DDATA3 DDATA1
TCLK/ P PSTCLK TDI/DSI R
R
D25
D24 SD_ VREF 2
D22
D18
BS2
CS0
VSS
U2RTS
U2TXD
PST2
PST0
T
VSS 1
D21 3
D17 4
SD_CS0 5
DDR_CLK DDR_CLK OUT OUT 6 7
TEA 8
U2RXD 9
PST3 10
PST1 11
VSS 16
T
Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 43
Pinout
7.2
196 MAPBGA Pinout
Figure 4 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages.
1 A NC 2 FEC0_ CRS FEC0_ RXD1 FEC0_ TXER FEC0_ TXD0 3 FEC0_ MDIO FEC0_ RXCLK FEC0_ TXEN FEC0_ TXD1 FEC0_ TXD2 4 U0RXD 5 U0TXD 6 U1RXD 7 I2C_SCL 8 A23 9 CS6 10 CS5 11 A15 12 A12 13 SD_ VREF 14 NC A
B
FEC0_ RXD2 FEC0_ TXCLK FEC0_ TXD3
FEC0_ COL FEC0_ RXDV FEC0_ RXD3 FEC0_ RXER
U0RTS
U1RTS
I2C_SDA
A22
A20
A16
A13
CS3
A9
TSIZ1
B
C
FEC0_ MDC FEC0_ RXD0
U0CTS
U1CTS
A21
A18
A17
A14
A10
A8
CS2
C
D
VDD
U1TXD
CS7
A19
CS4
A11
A7
A5
A2
D
E
DT0IN
DT0OUT
OVDD
OVDD
OVDD
SD_VDD2 SD_VDD2 SD_VDD2
A6
A4
A1
TSIZ0
E
F
DT1IN
DT1OUT
DT2IN
DT2OUT
OVDD
OVDD
VSS
VSS
SD_VDD2 SD_VDD2
A3
USB_CLK
A0
IRQ7
F
G
DT3OUT
DT3IN
SD_CAS
SD_WE
VDD
VSS
VSS
VSS
VSS
SD_VDD2
USB_ SPEED
VDD
IRQ6
IRQ5
G
H SD_SRAS
TS
SD_CS1
OE
SD_VDD1
VSS
VSS
VSS
VSS
OVDD
IRQ4
IRQ2
USB_RN
IRQ3
H
J
SD_CKE
SD_DQS3
D31
D22
SD_VDD1 SD_VDD1
VSS
VSS
OVDD
OVDD
USB_RP
USB_TP
IRQ1
USB_TN
J
K
BS3
D29
D28
D23
SD_VDD1 SD_VDD1 SD_VDD1
OVDD
OVDD
OVDD
TDO/DSO
RESET
USB_ TXEN
TA
K
L
D30
D26
D25
D24
BS2
R/W
VDD
PST2
DDATA0
QSPI_ DOUT
QSPI_CLK
RSTOUT
VSSPLL
USB_RXD L
M
D27
D21
D18
D17
SD_CS0
RCON
DDATA3
PST1
QSPI_ CS0 QSPI_ CS2
QSPI_DIN CLKMOD1
TDI/DSI
VDDPLL
EXTAL
M
N
D20
D19
D16
SD_A10
CS0
TEST
DDATA2
PST0
QSPI_ CS1 QSPI_ CS3 10
CLKMOD0 TMS/BKPT
USB_ SUSP
XTAL
N
P
NC 1
SD_ VREF 2
SD_DQS2 3
CS1 4
DDR_CLK DDR_CLK OUT OUT 5 6
PST3 7
DDATA1 8
CLKOUT 9
JTAG_EN 11
TCLK/PST TRST/DSC CLK LK 12 13
NC 14
P
Figure 4. MCF5274L and MCF5275L Pinout (196 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 44 Preliminary Freescale Semiconductor
Mechanicals
8
8.1
Mechanicals
Package Dimensions - 256 MAPBGA
Figure 6 shows MCF5275 256 MAPBGA package dimensions.
X Y
D
LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
M K A2 A1
256X
5 0.30 Z A
E
Z
4
0.15 Z DETAIL K
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS MIN MAX 1.25 1.60 0.27 0.47 1.16 REF 0.40 0.60 17.00 BSC 17.00 BSC 1.00 BSC 0.50 BSC
M 0.20
15X
e
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D E F G H J K L M N P R T
S
16151413121110 7654321
15X
e
S
256X
b 0.25 0.10
3
M M
ZXY Z
DIM A A1 A2 b D E e S
VIEW M-M
Figure 5. 256 MAPBGA Package Dimensions
8.2
Package Dimensions - 196 MAPBGA
Figure 6 shows MCF5275 196 MAPBGA package dimensions.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 45
Mechanicals
X Y
D Laser mark for pin 1 identification in this area K
M
NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
E DIM A A1 A2 b D E e S Millimeters Min Max 1.32 1.75 0.27 0.47 1.18 REF 0.35 0.65 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
M 0.20
13X
e Metalized mark for pin 1 identification in this area
A B C
S
14 13 12 11 10 9 6 5 4 3 2 1
S
13X
D E F G H J K L M N
5 A A2 0.30 Z
e
A1
Z
4
0.15 Z
Detail K Rotated 90 Clockwise
3
196X
P
b 0.30 Z X Y 0.10 Z View M-m
Figure 6. 196 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 46 Preliminary Freescale Semiconductor
Ordering Information
9
Ordering Information
Table 42. Orderable Part Numbers
Motorola Part Number MCF5274LVM133 MCF5274LVM166 MCF5274VM133 MCF5274VM166 MCF5275LCVM133 MCF5275LCVM166 MCF5275CVM133 MCF5275CVM166 Description MCF5274L RISC Microprocessor, 196 MAPBGA MCF5274L RISC Microprocessor, 196 MAPBGA MCF5274 RISC Microprocessor, 256 MAPBGA MCF5274 RISC Microprocessor, 256 MAPBGA MCF5275L RISC Microprocessor, 196 MAPBGA MCF5275L RISC Microprocessor, 196 MAPBGA MCF5275 RISC Microprocessor, 256 MAPBGA MCF5275 RISC Microprocessor, 256 MAPBGA Speed 133MHz 166MHz 133MHz 166MHz 133MHz 166MHz 133MHz 166MHz Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
10
Preliminary Electrical Characteristics
This appendix contains electrical specification tables and reference timing diagrams for the MCF5275 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5275. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this appendix supersede any values found in the module specifications.
10.1 Maximum Ratings
Table 43. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage I/O Pad Supply Voltage (3.3V) Memory Interface SSTL 2.5V Pad Supply Voltage Memory Interface SSTL 3.3V Pad Supply Voltage Clock Synthesizer Supply Voltage Digital Input Voltage 3 EXTAL pin voltage XTAL pin voltage Symbol VDD O VDD SD VDD SD VDD VDDPLL VIN VEXTAL VXTAL Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to + 2.8 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to + 4.0 0 to 3.3 0 to 3.3 Unit V V V V V V V V
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 47
Preliminary Electrical Characteristics
Table 43. Absolute Maximum Ratings1, 2
Instantaneous Maximum Current Single pin limit (applies to all pins) 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range ID TA (TL - TH) Tstg 25 - 40 to 85 - 65 to 150 mA C C
NOTES: 1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. 2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or O VDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to V SS and O VDD. 5 Power supply must maintain regulation within operating O V DD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the injection current may flow out of O VDD and could result in external power supply going out of regulation. Insure external O VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
10.2 Thermal Characteristics
Table 44 lists thermal resistance values
Table 44. Thermal characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature 256 MBGA Four layer board (2s2p) 256 MBGA Four layer board (2s2p) 256 MBGA 256 MBGA Natural convection 256 MBGA Symbol JMA JMA JB JC jt Tj Value 261,2 23 153 104 25 105 Unit C/W C/W C/W C/W C/W
oC
NOTES: 1 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 48 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
4
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D x JMA ) (1) Where: TA JMA PD PINT PI/O = Ambient Temperature, C = Package Thermal Resistance, Junction-to-Ambient, C/W = PINT + PI/O = IDD x VDD, Watts - Chip Internal Power = Power Dissipation on Input and Output Pins -- User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K / ( T J + 273C ) Solving equations 1 and 2 for K gives: K = PD x (TA + 273 C) + JMA x PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2)
10.3 ESD Protection
Table 45. ESD Protection Characteristics1, 2
Characteristics ESD Target for Human Body Model ESD Target for Machine Model HBM Circuit Description MM Circuit Description Number of pulses per pin (HBM) positive pulses negative pulses Number of pulses per pin (MM) positive pulses negative pulses Interval of Pulses Symbol HBM MM Rseries C Rseries C -- -- -- -- -- Value 2000 200 1500 100 0 200 1 1 -- 3 3 1 sec Units V V ohms pF ohms pF --
NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 49
Preliminary Electrical Characteristics
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
10.4 DC Electrical Specifications
Table 46. DC Electrical Specifications1
Characteristic Core Supply Voltage I/O Pad Supply Voltage SSTL I/O Pad Supply Voltage Input High Voltage Input Low Voltage Input High Voltage SSTL 2.5V I/O Pads Input Low Voltage SSTL 2.5V I/O Pads Input High Voltage SSTL 3.3V I/O Pads Input Low Voltage SSTL 3.3V I/O Pads Input Hysteresis Input Leakage Current Vin = VDD or VSS, Input-only pins High Impedance (Off-State) Leakage Current Vin = VDD or VSS, All input/output and output pins Output High Voltage (All input/output and all output pins) IOH = -2.0 mA Output Low Voltage (All input/output and all output pins) IOL = 2.0mA Weak Internal Pull Up Device Current, tested at VIL Max.2 Input Capacitance All input-only pins All input/output (three-state) pins Load Capacitance4 Low Drive Strength High Drive Strength Core Operating Supply Current 5 Master Mode WAIT DOZE STOP I/O Pad Operating Supply Current Master Mode Low Power Modes DC Injection Current 3, 6, 7, 8 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total MCU Limit, Includes sum of all stressed pins
3
Symbol VDD O VDD SD VDD VIH VIL VIH VIL VIH VIL VHYS Iin IOZ VOH VOL IAPU Cin
Min 1.35 3.0 2.3 0.7 x O VDD VSS - 0.3 2.0 - 0.5 2.0 - 0.5 0.06 x VDD -1.0 -1.0 O VDD - 0.5 __ -10 -- --
Max 1.65 3.6 2.7 3.6 0.35 x O VDD 2.8 0.8 3.6 0.8 -- 1.0 1.0 __ 0.5 - 130 7 7
Unit V V V V V V V V V mV A A V V A pF
pF CL IDD -- -- -- -- O IDD -- -- IIC -1.0 -10 1.0 10 250 250 mA A mA 175 15 10 100 mA mA mA A 25 50
NOTES: 1 Refer to Table 47 for additional PLL specifications. 2 Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 50 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
3 4 5 6 7 8
This parameter is characterized before qualification rather than 100% tested. pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. All functional non-supply pins are internally clamped to VSS and their respective VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
10.5 Oscillator and Phase Lock Loop (PLLMRFM) Electrical Specifications
Table 47. PLL Electrical Specifications1
Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 Mode (NOTE: fsys/2 = 2 x fref_1:1) Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency Loss of Reference Frequency 3, 5 Self Clocked Mode Frequency Crystal Start-up Time
5, 6 4, 5
Symbol fref_crystal fref_ext fref_1:1 fcore fsys/2 fLOR fSCM tcst VIHEXT VIHEXT VILEXT VILEXT VOH
Min 8 8 24 0 fref / 32 100 TBD -- TBD TBD TBD TBD TBD
Max 25 25 83 166 83 83 1000 TBD 10 TBD TBD
Unit MHz
MHz MHZ MHz kHz MHz ms V
EXTAL Input High Voltage Crystal Mode All other modes (Dual Controller (1:1), Bypass, External) EXTAL Input Low Voltage Crystal Mode All other modes (Dual Controller (1:1), Bypass, External) XTAL Output High Voltage IOH = 1.0 mA XTAL Output Low Voltage IOL = 1.0 mA XTAL Load Capacitance7 PLL Lock Time
8
V TBD TBD V -- V TBD 5 30 750 11 750 1 60 pF s ms s ns % fsys/2 --
VOL
tlpll Time 6, 9 tlplk
-- -- --
Power-up To Lock With Crystal Reference Without Crystal Reference10 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11 Duty Cycle of reference 5
tskew tdc
-1 40
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 51
Preliminary Electrical Characteristics
Table 47. PLL Electrical Specifications1
Characteristic Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Frequency Modulation Range Limit14, 15 (fsys/2Max must not be exceeded) ICO Frequency. fico = fref * 2 * (MFD+2)16
5, 6, 9,12, 13
Symbol fUL fLCK Cjitter
Min - 3.8 - 1.7 -- --
Max 4.1 2.0 5 .01 2.2 83
Unit % fsys/2 % fsys/2 % fsys/2 % fsys/2 MHz
Cmod fico
0.8 48
NOTES: 1 All values given are initial design targets and subject to change. 2 All internal registers retain data at 0 Hz. 3 "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications. 7 Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics. 8 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 9 Assuming a reference is available at power up, lock time is measured from the time V DD and VDDPLL are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. 10 t -6 lpll = (64 * 4 * 5 + 5 x ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and = 1.57x10 x 2(MFD + 2) 11 PLL is operating in 1:1 PLL mode. 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the jitter percentage for a given interval. 13 Based on slow system clock of 33MHz maximum frequency. 14 Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100KHz. 15 Modulation rate selected must not result in f sys/2 value greater than the fsys/2 maximum specified value. Modulation range determined by hardware design. 16 fsys/2 = fico / (2 * 2RFD)
10.6 External Interface Timing Characteristics
Table 48 lists processor bus input timings. NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 52 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 48. Processor Bus Input Timing Specifications
Name B0 CLKOUT Control Inputs B1a B1b B2a B2b Control input valid to CLKOUT BKPT valid to CLKOUT high
3
Characteristic1
Symbol tCYC
Min 12
Max Unit -- ns
high2
tCVCH tBKVCH tCHCII tBKNCH
9 9 0 0
-- -- -- --
ns ns ns ns
CLKOUT high to control inputs invalid2 CLKOUT high to asynchronous control input BKPT invalid3 Data Inputs
B4 B5
Data input (D[31:16]) valid to CLKOUT high CLKOUT high to data input (D[31:16]) invalid
tDIVCH tCHDII
4 0
-- --
ns ns
NOTES: 1 Timing specifications have been indicated taking into account the full drive strength for the pads. 2 TEA and TA pins are being referred to as control inputs. 3 Refer to figure A-19.
Timings listed in Table 48 are shown in Figure 7.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 53
Preliminary Electrical Characteristics * The timings are also valid for inputs sampled on the negative clock edge. CLKOUT (83MHz) TSETUP THOLD Invalid
Input Setup And Hold
Invalid
Valid
trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time Vh = VIH Vl = VIL
CLKOUT
B4 B5
Inputs
Figure 7. General Input Timing Requirements
10.7 Processor Bus Output Timing Specifications
Table 49 lists processor bus output timings.
Table 49. External Bus Output Timing Specifications
Name Characteristic Control Outputs B6a B6b B6c B7 B7a CLKOUT high to chip selects (CS[7:0]) valid 1 CLKOUT high to byte enables (BS[3:2]) valid2 tCHCV tCHBV tCHOV tCHCOI tCHCI -- -- -- 0.5tCYC + 1.5 0.5tCYC + 1.5 0.5tCYC + 5 0.5tCYC + 5 0.5tCYC + 5 -- -- ns ns ns ns ns Symbol Min Max Unit
CLKOUT high to output enable (OE) valid3 CLKOUT high to control output (BS[3:2], OE) invalid CLKOUT high to chip selects invalid
Address and Attribute Outputs B8 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid tCHAV -- 9 ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 54 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 49. External Bus Output Timing Specifications (continued)
Name B9 Characteristic CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid Data Outputs B11 B12 B13
1
Symbol tCHAI
Min 1.5
Max --
Unit ns
CLKOUT high to data output (D[31:16]) valid CLKOUT high to data output (D[31:16]) invalid CLKOUT high to data output (D[31:16]) high impedance
tCHDOV tCHDOI tCHDOZ
-- 1.5 --
9 -- 9
ns ns ns
NOTES: CS transitions after the falling edge of CLKOUT. 2 BS transitions after the falling edge of CLKOUT. 3 OE transitions after the falling edge of CLKOUT.
Read/write bus timings listed in Table 49 are shown in Figure 8, Figure 9, and Figure 10.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 55
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT B7a CSn A[23:0] TSIZ[1:0] TS TIP B8 B6c OE B7 B9 R/W (H) B6b BS[3:2] B4 D[31:16] B5 TA (H) B13 B7 B11 B12 B8 B6b B7 B0 B7a B6a B8 B9
B6a
B8
B8 B9 B8
B9 B9
TEA (H)
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 49.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 56 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics S0 CLKOUT CSn B6a
B7a
S1
S2
S3
S4
S5
S0
S1
B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP OE B6c B7 R/W (H) B9
B9
B9
BS[3:2]
B6b
B7 B5 B4
D[31:16] TA B1a B2a
TEA (H)
Figure 9. SRAM Read Bus Cycle Terminated by TA
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 49.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 57
Preliminary Electrical Characteristics
S0
CLKOUT CSn B6a
S1
S2
S3
S4
S5
S0
S1
B7a
B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP OE B6c B7 B9
B9
B9
R/W (H)
BS[3:2]
B6b
B7
D[31:16]
TA (H)
B1a TEA
B2a
Figure 10. SRAM Read Bus Cycle Terminated by TEA
10.8 DDR SDRAM AC Timing Characteristics
The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is available and is user programmable. DDR Clock timing specifications are given in Table 50 and Figure 11.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 58 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 50. DDR Clock Timing Specifications1
Symbol VMP VOUT VID VIX Characteristic Clock output mid-point voltage Clock output voltage level Clock output differential voltage (peak to peak swing) Clock crossing point voltage Min 1.05 -0.3 0.7 1.05 Max 1.45 SD VDD + 0.3 SD VDD + 0.6 1.45 Unit V V V V
NOTES: 1 SD VDD is nominally 2.5V.
SDCLK VIX VMP VIX SDCLK VID
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 51 must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 51. DDR Timing
NUM DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DD16 Characteristic1 Frequency of operation2 Clock Period (DDR_CLKOUT) Pulse Width High3 Pulse Width Low3 DDR_CLKOUT high to DDR address, SD_CKE, SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid DDR_CLKOUT high to DDR address, SD_CKE, SD_CS, SD_SCAS, SD_SRAS, SD_WE invalid Write command to first SD_DQS Latching Transition SD_DQS high to Data and DM valid (write) - setup4,5 SD_DQS high to Data and DM invalid (write) SD_DQS high to Data valid (read) - setup6 SD_DQS high to Data invalid (read) - hold7 SD_DQS falling edge to CLKOUT high - setup SD_DQS falling edge to CLKOUT high - hold DQS input read preamble width (tRPRE) DQS input read postamble width (tRPST) DQS output write preamble width (tWPRE) DQS output write postamble width (tWPST) hold4 tCK tCKH tCKl tCMV tCMH tDQSS tQS tQH tIS tIH tDSS tDSH tRPRE tRPST tWPRE tWPST Symbol Min TBD 12 0.45 0.45 2 1.5 1 0.25 x tCK+ 1 0.5 0.5 0.9 0.4 0.25 0.4 Max 83 TBD 0.55 0.55 0.5 x tCK + 1 1.25 1 1.1 0.6 -- 0.6 Unit MHz ns tCK tCK ns ns tCK ns ns ns ns ns ns tCK tCK tCK tCK
NOTES: 1 All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins. 2 DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core. 3 tCKH + tCKL must be less than or equal to tCK. 4 D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2. MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 59
Preliminary Electrical Characteristics
5
The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The remaining data beats will be valid for each subsequent SD_DQS edge 6 Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 7 Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data line becomes invalid.
Figure 13 shows a DDR SDRAM write cycle.
DDR_CLKOUT VIX VMP VIX DDR_CLKOUT
VID
Figure 12. DDR_CLKOUT and DDR_CLKOUT crossover timing
DD1 DDR_CLKOUT
DD2
DD3
DDR_CLKOUT
DD5 SD_CSn,SD_WE, SD_SRAS,SD_SCAS DD4 A[13:0]
CMD
DD6
ROW
COL
DD7
DM[3:2] DD8 SD_DQS[3:2] DD7 D[31:16]
WD1 WD2 WD3 WD4
DD8
Figure 13. DDR Write Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 60 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
DD1 CLKOUT
DD2
DD3 CLKOUT
DD5 SD_CSn,SD_WE, SD_SRAS,SD_SCAS DD4 A[13:0]
CL=2
CMD CL=2.5 ROW COL DQS Read Preamble
DD10 DD9
SD_DQS[3:2] CL = 2
DQS Read Postamble
D[31:16]
SD_DQS[3:2] CL = 2.5
WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble
D[31:16]
WD1 WD2 WD3 WD4
Figure 14. DDR Read Timing
10.9 General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1, Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in Table 52 and Figure 15.
Table 52. GPIO Timing
NUM G1 G2 G3 G4 Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min 1.5 9 1.5 Max 10 Unit ns ns ns ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 61
Preliminary Electrical Characteristics
CLKOUT
G1 G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 15. GPIO Timing
10.10 Reset and Configuration Override Timing
Table 53. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1 NUM R1 R2 R3 R4 R5 R6 R7 R8 Characteristic RESET Input valid to CLKOUT High CLKOUT High to RESET Input invalid RESET Input valid Time
2
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 0 20 0 -
Max 10 1 x tCYC
Unit ns ns tCYC ns ns tCYC ns ns
CLKOUT High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
NOTES: 1 All AC timing is shown with respect to 50% O VDD levels unless otherwise noted. 2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 62 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
CLKOUT
R1 R2 R3 R4 R4 R8 R5 Configuration Overrides1: (RCON, Override pins]) R6 R7
RESET
RSTOUT
1. Refer to the Coldfire Integration Module (CIM) section for more information.
Figure 16. RESET and Configuration Override Timing
10.11 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
10.11.1MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK)
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FECn_RXCLK frequency. Table 54 lists MII receive channel timings.
Table 54. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic FECn_RXD[3:0], FECn_RXDV, FECn_RXER to FECn_RXCLK setup FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV, FECn_RXER hold FECn_RXCLK pulse width high FECn_RXCLK pulse width low 5 5 35% 35% Min Max -- -- 65% 65% ns ns FECn_RXCLK period FECn_RXCLK period Unit
Figure 17 shows MII receive signal timings listed in Table 54.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 63
Preliminary Electrical Characteristics
M3
FECn_RXCLK (input)
FECn_RXD[3:0] (inputs) FECn_RXDV FECn_RXER M1 M2
M4
Figure 17. MII Receive Signal Timing Diagram
10.11.2MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK)
Table 55 lists MII transmit channel timings. The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FECn_TXCLK frequency. The transmit outputs (FECn_TXD[3:0], FECn_TXEN, FECn_TXER) can be programmed to transition from either the rising or falling edge of FECn_TXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it.
Table 55. MII transmit channel timings.
Num M5 M6 M7 M8 Characteristic FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER invalid FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER valid FECn_TXCLK pulse width high FECn_TXCLK pulse width low 5 -- 35% 35% Min Max -- 25 65% 65% ns ns FECn_TXCLK period FECn_TXCLK period Unit
Figure 18 shows MII transmit signal timings listed in Table 55.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 64 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
M7
FECn_TXCLK (input) M5 FECn_TXD[3:0] (outputs) M8
FECn_TXEN
FECn_TXER M6
Figure 18. MII Transmit Signal Timing Diagram
10.11.3MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
Table 56 lists MII asynchronous inputs signal timing.
Table 56. MII asynchronous input signal timing
Num M9 Characteristic FECn_CRS, FECn_COL minimum pulse width Min 1.5 Max -- Unit FECn_TXCLK period
Figure 19 shows MII asynchronous input timings listed in Table 56.
FECn_CRS, FECn_COL M9
Figure 19. MII Async Inputs Timing Diagram
10.11.4MII Serial Management Channel Timing (FECn_MDIO and FECn_MDC)
Table 57 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 57. MII serial management channel timings.
Num M10 M11 M12 M13 Characteristic FECn_MDC falling edge to FECn_MDIO output invalid (minimum propagation delay) Min 0 Max -- 25 -- -- ns ns ns ns Unit
FECn_MDC falling edge to FECn_MDIO output valid (max prop delay) -- FECn_MDIO (input) to FECn_MDC rising edge setup FECn_MDIO (input) to FECn_MDC rising edge hold 10 0
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Preliminary Electrical Characteristics
Table 57. MII serial management channel timings.
Num M14 M15 Characteristic FECn_MDC pulse width high FECn_MDC pulse width low Min 40% 40% Max 60% 60% Unit MDC period MDC period
Figure 20 shows MII serial management channel timings listed in Table 57.
M14 M15
FECn_MDC (output)
M10
FECn_MDIO (output)
M11
FECn_MDIO (input)
M12
M13
Figure 20. MII Serial Management Channel Timing Diagram
10.11.5USB Interface AC Timing Specifications
Table 58 lists USB Interface timings.
Table 58. USB Interface timings.
Num US1 US2 US3 US4 Characteristic USB_CLK frequency of operation USB_CLK fall time (VIH = 2.4 V to VIL = 0.5 V) USB_CLK rise time (VIL = 0.5 V to VIH = 2.4 V) USB_CLK duty cycle (at 0.5 x O VDD) Data Inputs US5 US6 USB_RP, USB_RN, USB_RXD valid to USB_CLK high USB_CLK high to USB_RP, USB_RN, USB_RXD invalid Data Outputs 6 6 -- -- ns ns Min 48 -- -- 45 Max 48 2 2 55 Units MHz ns ns %
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 66 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 58. USB Interface timings.
Num US7 US8 Characteristic USB_CLK high to USB_TP, USB_TN, USB_SUSP valid USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid Min -- 3 Max 12 -- Units ns ns
Figure 21 shows USB interface timings listed in Table 58.
US1
USB_CLK
US7
USB Outputs
US8
US5
USB Inputs
US6
trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time Vh = VIH Vl = VIL
Figure 21. USB Signals timing diagram
10.12 I2C Input/Output Timing Specifications
Table 59 lists specifications for the I2C input timing parameters shown in Figure 22.
Table 59. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I1 I2 I3 I4 I5 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Min 2 x tCYC 8 x tCYC -- 0 -- Max -- -- 1 -- 1 Units ns ns mS ns mS
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 67
Preliminary Electrical Characteristics
Table 59. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I6 I7 I8 I9 Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Characteristic Min 4 x tCYC 0 2 x tCYC 2 x tCYC Max -- -- -- -- Units ns ns ns ns
Table 60 lists specifications for the I2C output timing parameters shown in Figure 22.
Table 60. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I11 I2 1 I3 2 I4 1 I5
3
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 x tCYC 10 x tCYC -- 7 x tCYC -- 10 x tCYC 2 x tCYC 20 x tCYC 10 x tCYC
Max -- -- -- -- 3 -- -- -- --
Units ns ns S ns ns ns ns ns ns
I6 1 I7
1
I8 1 I9 1
NOTES: 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 60. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 60 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 59 and Table 60.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 68 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
I2 SCL
I6
I5
I1
I4
I7
I8
I3
I9
SDA
Figure 22. I2C Input/Output Timings
10.13 DMA Timers Timing Specifications
Table 61 lists timer module AC timings.
Table 61. Timer Module AC Timing Specifications
Name T1 T2 Characteristic 1 T0IN / T1IN / T2IN / T3IN cycle time T0IN / T1IN / T2IN / T3IN pulse width Min 3 x tCYC 1 x tCYC Max -- -- Unit ns ns
NOTES: 1 All timing references to CLKOUT are given to its rising edge.
10.14 QSPI Electrical Specifications
Table 62 lists QSPI timings.
Table 62. QSPI Modules AC Timing Specifications
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[3:0] to QSPI_CLK QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) Characteristic Min 1 -- 2 9 9 Max 510 10 -- -- -- Unit tCYC ns ns ns ns
The values in Table 62 correspond to Figure 23.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 69
Preliminary Electrical Characteristics
QS1 QSPI_CS[3:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 23. QSPI Timing
10.15 JTAG and Boundary Scan Timing
Table 63. JTAG and Boundary Scan Timing
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 x tCYC 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 3 33 33 26 8 Unit fsys/2 ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1 JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 70 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
J2 J3 J3
TCLK (input)
J4
VIH VIL J4
Figure 24. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 25. Boundary Scan (JTAG) Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 71
Preliminary Electrical Characteristics
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 26. Test Access Port Timing
TCLK
14
TRST
13
Figure 27. TRST Timing
10.16 Debug AC Timing Specifications
Table 64 lists specifications for the debug AC timing parameters shown in Figure 29.
Table 64. Debug AC Timing Specification
166 MHz Num D0 D1 D2 D3 D4
1
Characteristic Min PSTCLK cycle time PST, DDATA to CLKOUT setup CLKOUT to PST, DDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold 4 1.5 1 x tCYC 4 x tCYC Max 0.5
Units tCYC ns ns ns ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 72 Preliminary Freescale Semiconductor
Preliminary Electrical Characteristics
Table 64. Debug AC Timing Specification
166 MHz Num D5 D6 D7 D8 DSCLK cycle time BKPT input data setup time to CLKOUT Rise BKPT input data hold time to CLKOUT Rise CLKOUT high to BKPT high Z Characteristic Min 5 x tCYC 4 1.5 0.0 10.0 Max ns ns ns ns Units
NOTES: 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 28 shows real-time trace timing for the values in Table 64.
CLKOUT
D1
D2
PST[3:0] DDATA[3:0]
Figure 28. Real-Time Trace AC Timing
Figure 29 shows BDM serial port AC timing for the values in Table 64.
CLKOUT
D5
DSCLK
D3
DSI
Current
D4
Next
DSO
Past
Current
Figure 29. BDM Serial Port AC Timing
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Device/Family Documentation List
11
Device/Family Documentation List
Table 65. MCF5275 Documentation
Motorola Document Number MCF5275EC/D MCF5275RM/D MCF5275PB/D MCF5275FS CFPRODFACT/D MCF5XXXWP MAPBGAPP CFPRM/D Title MCF5275 RISC Microprocessor Hardware Specifications MCF5275 Reference Manual MCF5275 Product Brief MCF5275 Fact Sheet The ColdFire Family of 32-Bit Microprocessors Family Overview and Technology Roadmap MCF5XXXWP WHITE PAPER: Motorola ColdFire VL RISC Processors MAPBGA 4-Layer example ColdFire Family Programmer's Reference Manual Revision 0 0 0 0 0 0 0 2 Status This Document In Process Available In Process Available Available Available Available
12
Document Revision History
Table 66. Document Revision History
Rev. No. 1.1 1 0 Substantive Change(s) Removed duplicate information in the module description sections. The information is all in the Signals Description Table. Added Figure 6 Initial release.
Table 66 provides a revision history for this hardware specification.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 74 Preliminary Freescale Semiconductor
Document Revision History
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MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary 75
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MCF5275EC/D Rev. 1.1, 9/2004
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